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18- bit, 2 msps/1 msp s/500 ksps, precision, pseudo differential, sar ad cs preliminary technical data AD4002 / ad4006 / ad4010 rev. pra document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2017 analog devices, inc. all rights reserved. technical support www.analog.com features throughput: 2 msps/1 msps /500 ksps options inl: 2.0 lsb maximum guaranteed 1 8- bit , no missing codes low power 9.75 mw at 2 msps , 4.9 mw at 1 msps , 2.5 mw at 500 ksps (vdd only) 70 w at 10 ksps , 14 mw at 2 msps (total) s nr : 95 db typical at 1 khz , v ref = 5 v; tbd db typical at 100 k hz thd: ? 120 db typ ical at 1 khz , v ref = 5 v; tbd d b typical at 100 khz ease of use features reduce system power and complexity input overvoltage clamp circuit reduced n on linear input charge kick back high - z m ode long acquisition phase input span compression fast conversion time allows low spi clock rates spi - programmable modes, r ead/ w rite capability, s tatus w ord pseudo d ifferential (single - ended) analog input range 0 v to v ref with v ref from 2.4 v to 5.1 v single 1.8 v supply operation with 1.71 v to 5.5 v logic i nterface sar architecture: n o latency/pipeline delay, valid first conversion first accurate conversion guaranteed o pera tion: ?40c to + 125c spi - /qspi - /microwire - /dsp - compatible serial interface ability to daisy - chain multiple adcs and busy indicator 10- lead packages : 3 mm 3 mm lfcsp , 3 mm 4.90 mm msop applications automatic test equipment machine automation medical e quipment battery - powered equipment precision data acquisition systems general description the ad400 2 /ad400 6 /ad40 10 are low noise, low power, high speed , 18- bit, precision successive approximation register (sar) analog - to - digital converter s ( adc s). the a d400 2 , ad400 6, and ad40 10 offer 2 msps, 1 msps, and 500 ksps throughputs, respectively. they incorporate ease of use features that reduce signal chain power consumption , reduce signal chain complexity , and enable higher channel density. the high - z mode, co upled with a long acquisition phase, eliminates the need for a dedicated high power, high speed adc driver, thus broadening the range of low power precision amplifiers that can drive t hese adcs directly while still achieving optimum performance. the input span compression feature enables the adc driver amplifier and the adc to operate off common supply rails without the need for a negative supply while preserving the full adc code range. the low serial peripheral interface (spi ) clock rate requirement reduc es the digital input/output power consumption, broadens processor options , and simplifies the task of sending data across digital isolation. operating from a 1.8 v supply, the a d4002/ad4006/ad4010 sample an analog input (in+) from 0 v to v ref with respect to a ground sense (in?) with v ref ranging from 2.4 v to 5.1 v. the ad400 2 consumes only 14 mw at 2 msps with a minimum sck rate of 75 mhz in turbo mode ; the ad400 6 consumes only 7 mw at 1 msps ; and the ad40 10 consumes only 3.5 mw at 500 ksps. the AD4002/ad4006/ad4010 all achieve 2.0 lsb integral nonlinearity error ( inl ) maximum, no missing codes at 1 8 bits, and 95 db signal - to - no ise ratio ( snr ) for an input frequency (f in ) of 1 khz . the reference voltage is applied externally and can be set independently of the supply voltage. the spi - compatible versatile serial interface features seven different modes including the ability, using the sdi input, to daisy - chain several adcs on a single 3 - wire bus , and provides an optional busy indicato r. the ad400 2 /ad400 6 /a d40 10 are compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the ad400 2 /ad4006 are available in a 10 - lead msop and 10- lead lfcsp , and the ad40 10 is available in a 10 - lead lfcsp , with operation specified from ?40c to +125c . the devices are pin compatible with the 18 - bit, 2 msps ad4003 (see table 8 ).
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 function al block diagram .............................................................. 3 specifications ..................................................................................... 4 timing specifications .................................................................. 7 absolut e maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 11 terminology .................................................................................... 16 theory of operation ...................................................................... 17 circuit information .................................................................... 17 converter operation .................................................................. 18 transfer functions ...................................................................... 18 applications information .............................................................. 19 typical application diagrams .................................................. 19 analog inputs ............................................................................. 20 driver amplifier choice ........................................................... 21 ease of drive features ............................................................... 22 voltage reference input ............................................................ 23 power supply ............................................................................... 23 digital interface .......................................................................... 24 register read/write functionality ........................................... 25 status word ................................................................................. 27 cs mode, 3 - wire tur b o mo d e ................................................. 28 cs mode, 3 - wire without busy indicator ............................. 29 cs mode, 3 - wire with busy i ndicator .................................... 30 cs mode, 4 - wire tur b o mo d e ................................................. 31 cs mode, 4 - wire without busy indicator ............................. 32 cs mode, 4 - wire with busy indicator .................................... 33 daisy - chain mode ..................................................................... 34 layout guidelines ....................................................................... 35 evaluating the AD4002/ad4006/ad4010 performance ........ 35 outline dimensions ....................................................................... 36
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 3 of 36 functional block dia gram gnd in+ in? sdi sck sdo cnv AD4002/ ad4006/ ad4010 18-bit sar adc serial interface vio ref vdd v ref 0 v ref /2 high-z mode clamp span compression turbo mode status bits 2.4v to 5.1v 1.8v 10f 1.8v to 5v 3-wire or 4-wire spi interface (daisy chain, cs) 16233-001 f igure 1.
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 4 of 36 specifications vdd = 1.71 v to 1.89 v , vio = 1.71 v to 5.5 v , v ref = 5 v , all specifications t min to t max , high - z mode disabled, span compression disabled , turbo mode enabled, and s amp l ing frequency (f s ) = 2 msps for the ad400 2 , f s = 1 msps for the ad400 6 , and f s = 500 ksps for the ad40 10 , unless otherwise noted. table 1. parameter test conditions/comments min typ ma unit resolution 16 bi ts analog input voltage range in+ voltage (v in+ ) ? in? voltage (v in? ) 0 v ref v operating input voltage v in+ to gnd ?0.1 v ref + 0.1 v v in? to gnd ?0.1 + 0.1 v s pan compression enabled 0.1 v ref 0.9 v ref v analog input current acquisition phase, t = 25c 0.3 na h igh - z mode enabled, converting dc input at 2 msps 1 a throughput complete cycle AD4002 500 ns ad4006 1000 ns ad4010 2000 ns conversion time 270 290 320 ns acquisition phase 1 AD4002 290 ns ad4006 790 ns ad4010 1790 ns throughput rate 2 AD4002 0 2 msps ad4006 0 1 msps ad4010 0 500 ksps transient response 3 t bd ns dc accuracy no missing codes 1 8 bi ts integral nonlinearity error (inl) ? 2.0 tbd +2.0 lsb ? 3.8 tbd +3.8 ppm t = 0c to 85c tbd tbd tbd lsb differential nonlinearity error (dnl) t bd tbd tbd lsb transition noise 1.6 lsb zero error t bd t bd lsb zero error drift 4 t bd t bd ppm/c gain error t bd tbd tbd lsb gain error drift 4 t bd t bd ppm/c power supply sensitivity vdd = 1.8 v 5% t bd l sb 1/f noise 5 bandwidth = 0.1 hz to 10 hz 6 v p -p ac accuracy dynamic range 95.5 db total rms noise 30 v rm s f in = 1 khz, ?0.5 dbfs, v ref = 5 v signal -to - noise ratio (snr) t bd 95 db spurious - free dynamic range (sfdr) t bd db total harmonic distortion (thd) ? 120 db signal - to - noise - and - distortion ratio (sinad) tbd 94.5 db oversampled dynamic range o versampling ratio (osr) = 256, v ref = 5 v 119.5 db
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 5 of 36 parameter test conditions/comments min typ max unit f in = 1 khz, ?0.5 dbfs, v ref = 2.5 v snr t bd 88.5 db sfdr t bd db thd t bd db sinad tbd tbd db f in = 100 khz, ?0.5 dbfs, v ref = 5 v snr t bd db thd t bd db sinad t bd db f in = 400 khz, ?0.5 dbfs, v ref = 5 v snr tbd db thd t bd db sinad t bd db ?3 db input bandwidth 10 mh z aperture delay 1 ns aperture jitter 1 p s rms reference voltage range, v ref 2.4 5.1 v current v ref = 5 v ad400 2 2 msps 0.75 ma ad4006 1 msps 0.325 ma ad4010 500 ksps 0.185 ma input overvoltage clamp in+/in? current, i in+ /i in? v ref = 5 v 50 ma v ref = 2.5 v 50 ma v in+ /v in? at maximum i in+ /i in? v ref = 5 v 5.4 v v ref = 2.5 v 3.1 v v in+ / v in? clamp on/off threshold v ref = 5 v 5.25 5.4 v v ref = 2.5 v 2.68 2.8 v deactivation time 360 ns ref current at maximum i in+ v in+ > v ref 100 a digital inputs logic levels input low voltage, v il vio > 2.7 v ?0.3 + 0.3 vio v v i o 2.7 v ?0.3 + 0.2 vio v input high voltage, v ih vio > 2.7 v 0.7 vio vio + 0.3 v v io 2.7 v 0.8 vio v io + 0.3 v input low current, i il ?1 +1 a input high current, i ih ?1 +1 a input pin capacitance 6 pf digital outputs data format s erial 18 bits, straight binary pipeline delay c onversion results available immediately after completed conversion output low voltage, v ol i sink = 500 a 0.4 v output high voltage, v oh i source = ?500 a vio ? 0.3 v
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 6 of 36 parameter test conditions/comments min typ max unit power supplies vdd 1.71 1.8 1.89 v vio 1.71 5.5 v standby current vdd and vio = 1.8 v, t = 25c 1.6 a power dissipation v dd = 1.8 v, vio = 1.8 v , v ref = 5 v 10 k sps, high - z mode disabled 70 w 500 k sps, high - z mode disabled 3.5 4.2 mw 1 m sps, hi gh - z mode disabled 7 8.2 mw 2 m sps, high - z mode disabled 14 16 mw 500 k sps, high - z mode enabled 4 5 mw 1 msps, high - z mode enabled 8 9.9 mw 2 m sps, high - z mode enabled 16 19 mw vdd only 500 ksps, high - z mode disabled 2.5 mw 1 m sps, high -z mode disabled 4.9 mw 2 m sps, high - z mode disabled 9.75 mw ref only 500 ksps, high - z mode disabled 0.9 mw 1 m sps, high - z mode disabled 1.9 mw 2 m sps, high - z mode disabled 3.75 mw vio only 500 ksps, high - z mode disabled 0.1 mw 1 m sps, high - z mode disabled 0.2 mw 2 m sps, high - z mode disabled 0.5 mw energy per conversion 7 nj/sample temperature range specified performance t min to t max ?40 + 125 c 1 the acq uisition phase is the time available for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 2 msps for the ad400 2, 1 msps for the ad400 6 , and 500 ksps for the ad4010 . 2 a throughput rate of 2 msps can only be achieved with turbo mode enabled and a minimum sck rate of 7 5 mhz. refer to table 4 for the maximum achievable throughput for different modes of operation. 3 transient response is the time required for the ad c to acquire a full - scale input step to 0.5 lsb accuracy. 4 the minimum and maximum values are guaranteed by c haracterization, but not production tested. 5 see the 1/f noise plot in figure 23 .
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 7 of 36 timing specification s vdd = 1.71 v to 1.89 v, vio = 1.71 v to 5.5 v, v ref = 5 v, all specifications t min to t max , high - z mode disabled, span compression disabled, turbo mode enabled, and f s = 2 msps for the ad400 2 , f s = 1 m sps for the ad400 6 , and f s = 500 ksps for the ad40 10 , unless otherwise noted. see figure 2 for the timing voltage levels. table 2. digital interface timing parameter symbol min typ max unit conversion time cnv rising edge to data available t conv 270 290 320 ns acquisition phase 1 t acq ad400 2 290 ns ad400 6 790 ns ad40 10 1790 ns time between conversions t cyc ad400 2 500 ns ad400 6 1000 ns ad40 10 2000 ns cnv pul se width ( cs mode) 2 t cnvh 10 ns sck period ( cs mode) 3 t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck period (daisy - chain mode) 4 t sck vio > 2.7 v 20 ns vio > 1.7 v 25 ns sck low tim e t sckl 3 ns sck high time t sckh 3 ns sck falling edge to data remains valid delay t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv or sdi low to sdo d17 most significant bit ( msb ) val id delay ( cs mode) t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns cnv rising edge to first sck rising edge delay t quiet1 190 ns last sck falling edge to cnv rising edge delay 5 t quiet2 60 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 2 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sck valid hold time from cnv rising edge (daisy - chain mode) t hsckcnv 12 ns sdi valid setup time from sck rising edge (daisy - chain mode) t ssdisck 2 ns sdi valid hold time from sck rising edge (daisy - chain mode) t hsdisck 2 ns 1 the acquisition phase is the time avail able for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 2 msps for the ad400 2, 1 msps for the ad400 6 , and 500 ksps for the ad4010 . 2 for turbo mode, t cnvh must match the t quiet1 minimum. 3 a throughput rate of 2 msps can only be achieve d with turbo mode enabled and a minimum sck rate of 7 5 mhz. r efer to table 4 for the maximum achievable throughput for different modes of operation. 4 a 50% duty cycle is assumed for sck. 5 see figure 22 for sinad, snr, and enob vs. t quiet2 . x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 2.7v, x = 80, and y = 20; for vio > 2.7v, x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 1. 16233-002 f igure 2 . voltage levels for timing
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 8 of 36 table 3 . register read/write timing parameter symbol min typ max unit read/write operation cnv pulse width 1 t cnvh 10 ns sck period t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck low time t sck l 3 ns sck high time t sckh 3 ns read operation cnv low to sdo d17 msb valid delay t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns sck falling edge to data remains valid t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv rising edge to sdo high impedance t dis 20 ns write operation sdi valid setup time from sck rising edge t ssdisck 2 ns sdi valid hold time from sck rising edge t hsdisck 2 ns cnv rising edge to sck e dge hold time t hcnvsck 0 ns cnv falling edge to sck active edge setup time t scnvsck 6 ns 1 for turbo mode, t cnvh must match th e t quiet1 minimum. tabl e 4 . achievable throughput for different modes of operation parameter test conditions/comments min typ max unit throughput , cs mode 3- wire and 4 - wire turbo mode f sck = 100 mhz, vio 2.7 v 2 m sps f sck = 80 mhz, vio < 2.7 v 2 m sps 3- wire and 4 - wire turbo mode and six status bits f sck = 100 mhz, vio 2.7 v 2 m sps f sck = 80 mhz, vio < 2.7 v 1.78 m sps 3- wire and 4 - wire mode f sck = 100 mhz, vio 2.7 v 1.75 m sps f sck = 80 mhz, vio < 2.7 v 1.62 m sps 3- wire and 4 - wire mode and six status bits f sck = 100 mhz, vio 2.7 v 1.59 m sps f sck = 80 mhz, vio < 2.7 v 1.44 m sps
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 9 of 36 absolute maximum rat ings note that the input overvoltage clamp cannot sustain t he overvoltage condition for an indefinite amount of time. table 5. parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0.4 v or 130 ma 2 supply voltage ref , vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to + 2.1 v vdd to vio ?6 v to +2.4 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature soldering 260c reflow as per jedec j -std -020 esd ratings human body model 4 kv machine model 200 v field induced charged device model 1.25 kv 1 see the analog inputs section for an explanation of in+ and in?. 2 current condition tested over a 10 ms time interval. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) desig n and operating environment. careful attention to pcb thermal design is required. table 6 . thermal resistance pacage type 1 a 2 c 3 unit rm -10 147 38 c/w cp - 10 - 9 114 33 c/w 1 test condition 1: thermal impedance simulated val ues are based upon use of 2s2p jedec pcb. 2 ja is the natural convection junction - to - ambient thermal resistance measured in a one cubic foot sealed enclosure. 3 jc is the junction - to - case thermal resistance. esd caution
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 10 of 36 pin c onfigurations and function descript ions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 AD4002/ ad4006 top view (not to scale) 16233-003 fi gure 3 . 10 - lead msop pin configuration 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9 sdi 8 sck 7 sdo 6 cnv AD4002/ ad4006/ ad4010 top view (not to scale) notes 1. connect the exposed pad to gnd. this connection is not required to meet the specified performance. 16233-004 figure 4 . 10 - lead lfcsp pin configuration tabl e 7 . pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the v ref range is 2.4 v to 5.1 v. this pin is referred to the gnd pin and must be decoupled closely to the gnd pin with a 10 f , x7r ceramic capacitor. 2 vdd p 1.8 v power supply. the vdd range is 1.71 v to 1.89 v. bypass vdd to gnd with a 0.1 f ceramic capacitor. 3 in+ ai analog input. referred to analog ground sense pin (in ? ). the device samples the voltage differential between in+ and in ? on the leading edge on cnv. the operating input range of in+ ? in ? is 0 v to v ref . 4 in? ai analog input ground sense . connect this pin to the analog ground plane or to a remote sense ground. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the con versions and selects the interface mode of the device: daisy - chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in daisy - chain mode, the data is read when cnv is high. 7 sdo do serial d ata output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multi ple features. it selects the interface mode of the adc as follows : da isy -c hain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 1 8 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. with cnv low, the device can be programmed by clocking in a 1 8- bit word on sdi on the rising edge of sck. 10 vio p input/output interface digital power. nominall y , this pin is at the same supply as the host interface (1.8 v , 2.5 v, 3 v, or 5 v). bypass vio to gnd with a 0.1 f ceramic capacitor. n/a 2 epad p exposed pad (lfcsp only). connect the exposed pad to gnd. this connection is not required to meet the specified performance. 1 ai is analog input, p is power , di is digital input, and do is digital output. 2 n/a means not applicable.
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 11 of 36 typical performance characteristics vdd = 1. 8 v; vio = 3.3 v; v ref = 5 v ; t = 25 c , high - z mode disabled, span compression disabled, turbo mode enabled, and f s = 2 msps for the ad400 2 , f s = 1 msps for the ad400 6 , and f s = 500 ksps for the ad40 10 , unless otherwise noted. tbd figure 5 . inl vs. code for various temperatures, v ref = 5 v tbd figure 6 . inl vs. code for various temperatures, v ref = 2.5 v tbd figure 7 . inl vs. code, high - z and span compression modes enabled, v ref = 5 v tbd figure 8 . dnl vs. code for various temperatures, v ref = 5 v tbd figure 9 . dnl vs. code for various temperatures, v ref = 2.5 v tbd figure 10 . dnl vs. code, high - z and span compression modes enabled, v ref = 5 v
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 12 of 36 tbd figure 11 . histogram of a dc input at code center, v ref = 2.5 v and v ref = 5 v tbd figure 12 . 1 khz, 0.5 dbfs input tone fast fourier transform ( fft ), wide view, v ref = 5 v tbd figure 13 . 100 khz, 0.5 dbfs input tone fft, wide view tbd figure 14 . histogram of a dc input at code transition, v re f = 2.5 v and v ref = 5 v tbd figure 15 . 1 khz, 0.5 dbfs input tone fft, wide view, v ref = 2.5 v tbd figure 16 . 400 khz, 0.5 dbfs input tone fft, wide view
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 13 of 36 tbd figure 17 . snr, s inad, and effective number of bits (enob) vs. reference voltage, f in = 1 khz tbd figure 18 . snr, sinad, and enob vs. temperature, f in = 1 khz tbd figure 19 . snr vs. decimation rate for various input frequ encies, 2 msps tbd figure 20 . thd and sfdr vs. reference voltage, f in = 1 khz tbd figure 21 . thd and sfdr vs. temperature, f in = 1 khz tbd figure 22 . sinad, snr, and enob vs. t qu iet2
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 14 of 36 tbd figure 23 . 1/f noise for 0.1 hz to 10 hz bandwidth, 50 ksps, 2500 samples averaged per reading tbd figure 24 . operating current vs. temperature, AD4002 , 2 msps tbd figure 25 . operating current vs. temperature, ad4010 , 500 ksps tbd figure 26 . zero error and gain error vs. temperature tbd figure 27 . operating current vs. temperature, ad4006 , 1 msps tbd figure 28 . reference current vs. reference voltage
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 15 of 36 tbd figure 29 . standby current vs. temperature tbd figure 30 . t dsdo vs. load capacitance
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 16 of 36 terminology integral nonlinearity error (inl) inl is the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond t he last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 32). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal voltage that results in the first code transition (1/2 ls b above analog ground) and the actual voltage producing that code. gain error the first transition (from 100 ... 00 to 100 ... 01) occurs at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) occurs for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transitio n from the difference between the ideal levels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between t he root mean square ( rms ) amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows: enob = ( sinad db ? 1.76)/6.02 enob is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ra tio of the rms value of the full scale to the total rms noise measured. the value for dynamic range is expressed in decibels. it is measured with a signal at ?60 dbfs so that it includes all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion ratio (sinad) sina d is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to acquire a full - scale input step to 0.5 lsb accuracy. power supply rejection ratio (psrr) psrr is the ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave applied to the adc vdd supply of frequency, f. psrr (db) = 10 log( p vdd_in / p ad c_out ) where: p vdd_in is the power at the frequency, f, at the vdd pin. p adc_out is the power at the frequency, f, in the adc output.
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 17 of 36 theory of operation comp control logic switches control busy output code cnv c c 2c 65,536c 4c 131,072c lsb sw+ msb lsb sw? msb c c 2c 65,536c 4c 131,072c in+ ref gnd in? 16233-007 f igure 31 . adc simplified schematic circuit information the ad400 2 /ad4 006 /ad40 10 are high speed , low power, single- supply, precise, 1 8- bit pseudo differential adc s based on a sar architecture. the ad400 2 is capable of converting 2,000,000 samples per second (2 msps) , the ad400 6 is capable of converting 1,000,000 samples per second (1 msps) , and the ad40 10 is capable of converting 500,000 samples per second (500 ksps). the power consumption of the ad400 2 /ad400 6 /ad40 10 sca les with throughput because the devices power down in between conversions. when operating at 10 ksps, for example, they typically consume 70 w, making them ideal for battery - powered applications . the ad400 2 /ad400 6 /ad40 10 also have a valid first conversion after being powered down for long periods , which can further reduce power consumed in applications in whi ch the adc does not need to be constantly converting. the ad400 2 /ad400 6 /ad40 10 provide the user with an on - chip track - and - hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. the ad400 2 /ad400 6 /ad40 10 incorp orate a multitude of unique ease of use features that result in a lower system power and footprint. the ad400 2 /ad400 6 /ad40 10 each have an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. the analog input incorpo rates circuitry that reduces the non linear charge kickback seen from a typical switched capacitor sar input. this reduction in kickback, combined with a longer acquisition phase , means reduced settling requirements on the driving amplifier. this combinatio n allows the use of lower bandwidth and lower power amplifiers as drivers. it has the additional benefit of allowing a larger resistor value in the input rc filter and a corresponding smaller capacitor , which results in a smaller rc load for the amplifier , improving stability and power dissipation. h igh -z mode can be enabled via the spi interface by programming a register bit (see table 14 ). when h igh - z m ode is enabled , the adc input has a low input charging current at low input si gnal frequencies as well as improved distortion over a wide frequency range up to 100 khz . for frequencies greater than 100 khz and multiplexing , disable high -z mode . for single - supply applications , a span compression feature creates additional headroom an d footroom for the driving amplifier to access the full range of the adc. the fast conversion time of the ad400 2 /ad400 6 /ad40 10, along with turbo mode , allow s low clock rates to read back conversions , even when running at their respective maximum throughput rates . note that , for the ad400 2 , the full throughput rate of 2 msps can be achieved only with turbo mode enabled . the ad400 2 /ad400 6 /ad40 10 can interface with any 1.8 v to 5 v digital logic family. they are available in a 10 - lead msop or a tiny 10 - lead lf csp that allows space savings and flexible configurations. the ad400 2 /ad400 6 /ad40 10 are pin for pin compatible with some of the 14- /16 -/18- /20 - bit precision sar adcs listed in table 8 . ta ble 8 . msop, lfcsp 14 - /16 - /18 - /20 - bit precision sar adcs bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps 20 1 a d4020 2 18 1 ad7989 - 1 2 ad7 691 2 ad4011 2 , ad7690 2 , ad7989-5 2 ad4003 2 , ad4007 2 , ad7982 2 , ad7984 2 18 3 a d4010 2 AD4002 2 , ad4006 2 16 1 ad7684 ad7687 2 ad7688 2 , ad7693 2 , ad7916 2 ad4001 2 , ad4005 2 , ad7915 2 16 3 ad7680 , ad7683 , ad7988-1 2 ad7685 2 , ad7694 ad7686 2 , ad7988-5 2 , ad4008 2 ad4000 2 , ad4004 2 , ad7980 2 , ad7983 2 14 3 ad7940 ad7942 2 ad7946 2 not applicable 1 true differential. 2 pin for pin compatible. 3 pseudo differentia l.
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 18 of 36 converter operation the ad400 2 /ad400 6 /ad40 10 are sar - based adc s using a charge redistribution sampling digital - to - analog - converter ( dac ). figure 31 shows the simplified schematic of the adc. the capacitive da c consists of two identical arrays of 1 8 binary weighted capacitors, which are connected to the comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via the sw+ and sw? switches . all independent switches connect the other terminal of each capacitor to the analog inputs. t he capacitor arrays are used as sampling capacitors and acquire the analog si gnal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase initiate s . when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. the differential voltage betwee n the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and v ref , the comparator input varies by bi nary weighted voltage steps ( v ref /2, v ref /4 , , v ref / 262,144 ). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the ad c output code and a busy signal indicator. because the AD4002 / ad4006 / ad4010 have on - board conversion clock s , the serial clock, sck, is not required for the conversion process. transfer functions the ideal transfer characteristic s for the a d400 2 /ad400 6 /ad40 10 are shown in figure 32 and table 9 . 000...000 000...001 000...010 111...101 111...110 111...111 adc code (straight binary) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 16233-008 f igure 32 . adc ideal transfer function (fsr is full - scale range) table 9. o utput codes and ideal input voltages description analog input, v ref = 5 v v ref = 5 v with span compression enabled (v) digital output code (hex) fsr ? 1 lsb 4.999981 v 4.499985 0x3ffff 1 midscale + 1 lsb 2.500019 v 2.500015 0x20001 midscale 2.5 v 2.5 0x20000 midscale ? 1 lsb 2.499981 v 2.499985 0x1ffff ?fsr + 1 lsb 19.07 v 0.50001526 0x00001 ?fsr 0 v 0.5 0x00000 2 1 this outpu t code is also the code for an overranged analog input ( v in+ ? v in? above v ref with span compression disabled and above 0.9 v ref with span compression enabled ). 2 this output code is also the code for an underranged analog input (v in+ ? v in? below 0 v wi th span compression disabled and below 0.1 v ref with span compression enabled ).
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 19 of 36 applications informa tion typical application diagrams figure 33 shows an example of the recommended connection diagram for the a d400 2 /ad400 6 /ad40 10 when multiple supplies are available. this configuration is used for best performance because the amplifier supplies can be selected to allow the maximum signal range. figure 34 shows a recomme nded connection diagram when using a single - supply system. this setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. c r v+ ref vdd vio gnd in+ in? sdi sck sdo cnv AD4002/ ad4006/ ad4010 2 3-wire/4-wire interface 1.8v 1.8v to 5v v+ +6.5v digital host (microprocessor/ fpga) v? ?0.5v host supply 100nf 100nf 5v v? amp v ref 0v v cm = v ref /2 ref 1 ldo amp v cm = v ref /2 10f 10k 10k 16233-009 f igure 33 . typical application diagram with multiple supplies c r ref vdd vio gnd in+ in? sdi sck sdo cnv AD4002/ ad4006/ ad4010 2 1.8v 1.8v to 5v v+ = 5v digital host (microprocessor/ fpga) host supply 100nf 100nf 4.096v amp 0.9 v ref 0.1 v ref v cm = v ref /2 ref 1 ldo amp v cm = v ref /2 10f 1 10k 10k 3-wire/4-wire interface 3 1 see the voltage reference input section for reference selection. c ref is usually a 10f ceramic capacitor (x7r). 2 span compression mode enabled. 3 see table 10 for rc filter and amplifier selection. 16233-010 f igure 34 . typical application diagram with a single supply
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 20 of 36 analog inputs figure 35 shows an equivalent circuit of the analog input structure , in cluding the overvoltage clamp of the AD4002/ad4006/ad4010 . c ext r ext v in ref d1 in+ gnd clamp 0v to 15v r in c in d2 c pin 16233-035 f igure 35 . equivalent analog input circuit input overvoltage clamp circuit most adc analog inputs, in+ and in? , have no overvoltage protection circuitry apart from esd pr otection diodes. during an overvoltage event, an esd protection diode from an analog input pin (in+ or in?) to ref forward biases and shorts the input pin to ref , potentially overload ing the reference or causing damage to the device . the ad400 2 /ad400 6 /ad40 10 internal overvoltage clamp circuit with a larger external resistor (r ext = 200 ?) eliminates the need for external protection diodes and protects the adc inputs against dc overvoltages. in applications where the amplifier rails are greater than v ref and less than ground , it is possible for the output to exceed the input voltage range of the device . in this case, the ad400 2/ ad400 6 /ad40 10 internal voltage clamp circuit en sure s that the voltag e on the input pin does not exceed v ref + 0.4 v and prevents dam age to the device by clamping the input voltage in a safe operating range and avoiding disturbance of the reference , which is particularly important for systems that share the reference among multiple adcs. if the analog input exceeds the reference voltage by 0.4 v, t h e internal clamp circuit turn s on and the current flow s through the clamp into ground, preventing the input from rising further and potentially causing damage to the device . the clamp turns on before d1 ( see figure 35) and can sink up to 50 ma of current. when the clamp is active, it sets the ov clamp flag bit in the register that can be read back (see table 14 ), which is a sticky bit that must be read to be c leared. the status of the clamp can also be checked in the status bits using an overvoltage clamp flag (see table 15 ). the clamp circui t does not dissipate static power in the off state. note that the clamp cannot sustain the overvoltage condition for an indefinite amount of time. the external rc filter is usually present at the adc input to band limit the input signal. during an overvoltage event, excessive voltage is dropped across r ext , and r ext becomes part of a protection circuit. the r ext value c an vary from 200 ? to 20 k? for 15 v protection. the c ext value can be as low as 100 pf for correct operation of the clamp. see table 1 for input overvoltage clamp specification s. the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. by using in? to sense a remote signal ground, ground potential difference s between the sensor and the local adc ground are eliminated. switched capacitor input during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor c pin and the network formed by the s eries connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 40 pf and is mainly the adc sampling capacitor. d uring the conversion phase , in which the switches are open , the input impedance is limited to c pin . r in and c in make a single - pole, low - pass filter that reduces undesirable aliasing effects and limits noise. rc f ilter v alues the rc filter value (represente d by r and c in figure 33 and figure 34 ) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full throughput. lower input signal bandwidth means that the rc cutoff can be lower, thereby reducing noise into the converter. for optimum performance at various throughputs, use the recommended rc values (200 ?, 180 pf) and the ada4807 -1. the rc values shown in table 10 are chosen for ease of drive considerations and greater adc input protection. the combi - nation of a large r value (200 ?) and small c value result s in a reduced dynamic load for the amplifier to drive. the smal ler value of c means fewer stability a nd phase margin concerns with the amplifier. the large value of r limits the current into the adc input when the amplifier output exceeds the adc input range. ta ble 10 . rc filter and amplifier selection for various input bandwidth s input signal bandwidth (khz) r (?) c (pf) recommended amplifier <10 s ee the high - z m ode section <200 200 180 ada4807-1 >200 200 120 ada4897-1 multiplexed 200 120 ada4897 - 1
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 21 of 36 driver amplifier cho ice although the ad400 2 /ad400 6 /ad40 10 are easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kep t l ow enough to preserve the snr and transition noise performance of the ad400 2 /ad400 6 /ad40 10 . the noise from the driver is filtered by the single- pole, low - pass f ilter of the analog input circuit made by r in and c in , or by the external filter, if one is used. because the typical noise of the ad400 2 /ad400 6 /ad40 10 is 30 v rms, the snr degradation due to the amplifier is ( ) ( ) ( ) ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3 2 2 v 30 v 30 log20 n db loss ne f snr ee f ?3 db is the i nput bandwidth, in megahertz, of the AD4002 / ad400 6/ ad40 10 ( 10 mhz) or the cutoff frequency of the input filter, i f one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver must have a thd performance commensurate with the ad400 2/ ad400 6/ ad40 10. ? for multichannel multiplexed applications, the driver amplifier and the analog input circuit of the ad400 2/ ad400 6/ ad40 10 must settle for a full - scale ste p onto the c apacitor array at a n 18- bit level ( 0.000191 %, 1.91 ppm ). in the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. this settling may differ significantly from the settling time at a n 18- bit l evel and must be verified prior to driver selection. high frequency input signals the ad400 2 /ad400 6 /ad40 10 ac performance over a wide input frequency range using a 5 v reference voltage is shown in figure 36 and figure 37. unlike other traditional sar adcs, the ad400 2 /ad400 6 /ad40 10 maintain exceptional ac perfor - mance for input frequencies up to the nyquist frequency with minimal performance degradation . note that the input frequency is limited to the nyquist frequency of the sample rate in use . tbd f igure 36 . snr, sinad, and enob vs. input frequency, vdd = 1.8 v, vio = 3.3 v, v ref = 5 v , 25c tbd f igure 37 . thd and sfdr vs. input frequency, vdd = 1.8 v, vio = 3.3 v, v ref = 5 v , 25c multiplexed applications the ad400 2 /ad400 6 /ad40 10 significantly reduce system complexity and cost for multiplexed applications that require superior performance in terms of noise, power, and through put. figure 38 shows a simplified block diagram of a multiplexed data acquisition system including a multiplexer, an adc driver, and the precision sar adc. sar adc adc driver multiplexer sensors r r r c c c c 16233-0 11 f igure 38 . multiplexed data acquisition signal chain using the AD4002/ad4006/ad4010
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 22 of 36 switching multiplexer channels typically results in large voltage steps at the adc inputs. to ensure an accurate conversion result , the step must be given adequate time to settle before the adc s amples its inputs (on the rising edge of cnv). the settling time error is dependent on the drive circuitry (multiplexer and adc driver), rc filter values, and the time when the multiplexer channels are switched. switch the multiplexer channels immediately after t quiet1 has elapsed from the start of the conversion to maximize settling time while preventing corruption of the conversion result. to avoid conversion corruption, do not switch the channels during the t quiet1 time. if the analog inputs are multiple xed during the quiet conversion time (t quiet1 ), the current conversion may be corrupted. ease of drive featur es input span compression in single - supply applications , it is desirable to use the full range of the adc ; h owever , the amplifier can have some he adroom and footroom requirements , which can be a problem , even if it is a rail - to - rail input and output amplifier. the ad400 2/ ad400 6/ ad40 10 include a span compression feature, which increases the headroom and footroom available to the amplifier by reducin g the input range by 10% from the top and bottom of the range while still accessing all available adc codes ( see figure 39) . the snr decrease s by approximately 1.9 db (20 l og( 8/10 )) for the reduced input range wh en span compression is enabled. span compression is disabled by default but can be enabled by writi ng to the relevant register bit ( see the digital interface section ). adc v ref = 4.096v digital output all 2 n codes +fsr ?fsr 90% of v ref = 3.69v 10% of v ref = 0.41v analog input 5v in+ 16233-300 f igure 39 . span c om pression high - z m ode the ad400 2 /ad400 6 /ad40 10 incorporate high - z mode , which reduces the non li near charge kickback when the capacitor dac switches back to the input at the start of acquisition . figure 40 shows the input current of the ad400 2 /ad400 6 /ad40 10 with h igh - z mode enabled and disabled. the low input current makes the adc easier to drive than the traditional sar adcs available in the market , even wi th high - z mode disabled. the input current reduces further t o submicroampere range when high - z mode is enabled. the high - z mode is disabled by default but can be enabled by writing to the register (see table 14 ). disable high - z mode for input frequencies above 100 khz or when multiplexing. tbd f igure 40 . input current vs. input differential voltage, vdd = 1.8 v, vio = 3.3 v, v ref = 5 v , 25c t o achieve the optimum data sheet performance from high resolution precision sar adc s, system designers are often forced to us e a dedicated high power, high speed amplifier to drive the traditional switched capacitor sar adc inputs for their precision applications , which is common ly encountered in designing a precision data acquisition signal chain. the benefits of high - z mode ar e low input current for slow (<10 k hz) or dc type signals and improved distortion (thd) performance over a frequency range of up to 100 khz. high - z mode allows a choice of lower power and lower bandwidth precision amplifiers with a lower rc filter cutoff t o drive the adc , removing the need for dedicated high speed adc drivers, which saves system power, size , and cost in precision, low bandwidth applications. high - z mode allows the amplifier and rc filter in front of the adc to be c hosen based on the signal bandwidth of interest and not based on the settling requirements of the switched capacitor sar adc inputs. additionally , the ad400 2 /ad400 6 /ad40 10 can be driven with a much higher source impedance than traditional sars , which means the resistor in the rc f ilter can have a value 10 times larger than p revious sar designs and with h igh -z mode enabled can tolerate even larger impedance. figure 41 shows the thd performance for various source impedances with high - z mode d isabled and enabled. tbd f igure 41 . thd vs. input frequency for various source impedances, vdd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 23 of 36 figure 42 and figure 43 show the ad400 2 /ad400 6 /ad40 10 snr and thd performance using the ada4077 -1 ( supply current per amplifier ( i sy ) = 400 a), and ada4610 -1 (i sy = 1.5 0 ma) precision amplifiers when driving the ad400 2 /ad400 6/ ad40 10 at full throughput for h igh - z mode both enabled and disabled with various rc filter values. these amplifiers achieve tbd db to tbd db typical sn r and close to tbd db typical tbd with high - z enabled for a 2.27 mhz rc bandwidth. thd is approximately tbd db better with high - z mode enabled, even for large r values greater than 200 ?. snr maintains close to tbd d b even with a very low rc filter cutoff . when high - z mode is enabled, the adc consumes approximately 2 mw per msps extra power; however, this is still significantly lower than using dedicated adc drivers like the ada4807 -1 . for any system, the front end usually limits the overall ac/dc performance of the signal chain. it is evid ent from the data sheet s of the selected precision amplifiers shown in figure 42 and figure 43 that their own noise and distortion performance dominates the snr and thd spe cification at a certain input frequency. tbd f igure 42 . snr vs. rc filte r bandwidth s for various precision adc drivers, f in = 1 khz (turbo mode on, high - z enabled/disabled) , vdd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c tbd f igure 43 . thd vs. rc bandwidth s for various precision adc drivers, f in = 1 khz (turbo mode on, high - z enabled/disabled) , vdd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c long acquisition phase the ad400 2 /ad400 6 /ad40 10 also feature a very fast c onversion time of 2 90 ns , which results in a long acquisition phase. the acquisition is further extended by a key feature of the ad400 2 /ad400 6 /ad40 10: the adc returns to the acquisition phase typically 100 ns before the end of the conversion . this feature provides an even longer time for the adc to acquire the new input voltage. a longer acquisition phase reduces the settling requirement on the driving amplifier , and a lower power/ bandwidth amplifier can be chosen. the longer acquisition phase means that a lower rc filter ( represented by r and c in figure 33 and figure 34) cutoff can be used , which means a noisier amplifier can also be tolerated. a larger value of r can be used in the rc filter with a corresponding smaller value of c , reducing amplifier stability concerns without affecting distortion performance significantly. a larger value of r also results in reduced dynamic power dissipation in the amplifier. see table 10 for details on setting the rc filter bandwidth and choosing a suitable amplifier. voltage reference in put a 10 f (x7r, 0805 size) ceramic chip capacitor is appropriate for the optimum performance of the reference input. for high er performance and lower drift, use a reference such as the adr4550 . u se a low power reference such as the adr3450 at the expense of a slight decrease in the noise performance . it is recommended to use a reference buffer such as the ada4807 -1 between the reference and the adc reference input. it is important to consider the optimum capacitance necessary to keep the reference buffer stable as well as to meet the minimum adc requirement stated previously in this section (t hat is, a 10 f ceramic chip capacitor, c ref ). power supply the ad400 2 /ad400 6/ ad40 10 use two power supply pins: a core supply (vdd) and a digital input/output interface supply (vio). vio allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio and vdd can be tied together for 1.8 v operation. the adp7118 low noise , cmos, low drop out (ldo) linear regulator is recommended to power the vdd and vio pins . the ad400 2 /ad400 6 /ad40 10 are independent of power supply sequen cing between vio and vdd. additionally, the ad400 2 /ad400 6 /ad40 10 are insensitive to power supply variations over a wide frequency range, as shown in figure 44.
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 24 of 36 tbd f igure 44 . psrr vs. frequ ency , vdd = 1.8 v, vio = 3.3 v, v ref = 5 v, 25c the AD4002/ad4006/ad4010 power down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this feature makes the device ideal for low sampling rates (even a few samples per second ) and battery - powered applications. figure 45 shows the AD4002 / ad4006 / ad4010 total power dissipation and individual power dissipation for each rail. tbd f igure 45 . power dissipation vs. throughput, vdd = 1.8 v, vio = 1.8 v, v ref = 5 v , 25c digital interface although the ad400 2 /ad400 6 /ad40 10 have a reduced number of pins, they offer flexibility in their serial interface modes. the ad400 2 /ad400 6 /ad40 10 can also b e programmed via 16 - bit spi writes to the configuration registers. when in cs mode, the ad400 2 /ad400 6 /ad40 10 are compatible with spi, qspi ?, microwire?, digital hosts, and digital signal processors ( dsps ) . in this mode, the ad400 2 /ad 4006 /ad40 10 can use either a 3 - wire or 4 - wire interface. a 3 - wire interface using the cnv, sck, and sdo signals minimizes wiring con - nections , which is useful, for instance, in isolated applications. a 4- wire interface using the sdi, cnv, sck, and sdo sign als allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this interface is useful in low jitter sampling or simultaneous sampling applications. t he ad400 2 /ad400 6 /ad40 10 provide a daisy - chain feature using the sdi inp ut for cascading multiple adcs on a single data line , similar to a shift register. the mode in which the device operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and daisy - chain mo de is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, daisy - chain mode is always selected. in either 3 - wire or 4 - wire mode, the ad400 2 /ad400 6 /ad40 10 offer the option of forcing a start bit in front of the dat a bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled in cs mode if cnv or sdi is low when the adc conversion ends. the state of sdo on power - up is either low or high -z, depending on the states of cnv and sdi , as shown in in table 11 . table 11 . state of sdo on power -up cnv sdi sdo 0 0 low 0 1 low 1 0 low 1 1 high -z the ad400 2 /ad400 6 /ad40 10 have turbo mode capability in both 3- wire and 4- wire mode. turbo mode is enabled by writing to the configura tion regis ter and replaces the busy indicator feature when enabled. turbo mode allows a slower spi clock rate , making interfacing simpler. t he maximum throughput of 2 msps for the ad400 2 can be achieved only with turbo mode enabled and a minimum sck rate of 75 mhz . the sck rate must be sufficiently fast to ensure the conversion result is clocked out before another conversion is initiated. the minimum required sck rate for an application can be derived based on the sample period (t cyc ), the number of bits that must b e read (including data and optional status bits), and which digital interface mode is used. timing diagrams and explanations for each digital interface mode are given in the digital modes of operation sections (see the cs mode, 3 - wire tur b o mo de section through the daisy - chain mode section). status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration regis ter. there are six status bits in total , as shown in table 15. the ad400 2 /ad400 6 /ad40 10 are configured by 16 - bit spi writes to the desired configuration register. the 16 - bit word can be written via the sdi line whi le cnv is held low. the 16 - bit word consists of an 8 - bit header and 8 - bit register data. for isolated systems, the adum141d is recommended, which can support the 75 mhz sck rate requir ed to run the AD4002 at its full throughput of 2 msps .
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 25 of 36 register read/write functionality the ad400 2 /ad400 6 /ad40 10 register bits are programmable and their default statuses are shown in table 12 . the register map is shown in tabl e 14 . the overvoltage clamp flag ( ov ) is a read only sticky bit , and it is cleared only if the register is read and the overvoltage condition is no longer present. it gives an indication of overvo ltage condition when it is set to 0 . table 12 . register bits register bits default status overvoltage ( ov ) c lamp f lag 1 bit , 1 = inactive (default ) span c ompression 1 bit , 0 = disable d (default ) high -z m ode 1 bit, 0 = disabled (default) turbo m ode 1 bit, 0 = disabled (default) enable s ix s tatus b its 1 bit, 0 = disabled (default) all access to the register map must start with a write to the 8 -b it command register in the spi interface block. the AD4002 / ad400 6/ ad4010 ignore all 1s until the first 0 is clocked in; the value loaded into th e command register is always a 0 followed by seven command bits. this command determines whether that operation is a write or a read. the ad400 2/ ad400 6/ ad40 10 command register is shown in tabl e 13. all register read/writes must occur while cnv is low. data on sdi is clocked in on the rising edge of sck. data on sdo is clocked out on the falling edge of sck. at the end of the data transf er , sdo is put in a high impedance state on the rising edge of cnv if daisy - chain mode is not enabled . if daisy - chain mode is enabled , sdo goes low on the rising edge of cnv. register reads are not allowed in daisy - chain mode. a register write requires thr ee signal lines: sck, cnv, and sdi. during a register write, to read the current conversion results on sdo, the cnv pin must be brought low after the conversion is completed; otherwise, the conversion results may be incorrect on sdo . h owever, the register write occur s regardless . the lsb of each configuration register is reserved because a user reading 16 - bit conversion data may be limited to a 16 - bit spi frame. the state of sdi on the last bit in the sdi frame may be the state that then persists when cnv r ises. because interface mode is partly set based on the sdi state when cnv rises, in this scenario, the user may need to set the final sdi state. the timing diagram s in figure 46 through fi gure 48 show how data is read and w ritten when the ad400 2 /ad400 6 /ad40 10 are configured in register read, write , and daisy - chain mode. ta ble 13 . command register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wen r/ w 0 1 0 1 0 0 ta ble 14. register map addr[1:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0x0 reserved reserved reserved enable six status bits span compression high -z mode turbo mode overvoltage ( ov ) clamp flag (read only sticky bit ) 0xe1 t cyc t sck t dis t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh t en cnv sck 1 2 3 4 5 6 7 0 1 1 0 1 0 1 0 0 b0 b1 b2 b3 b4 b5 b6 wen r/w 0 1 0 1 addr[1:0] 8 9 10 11 12 13 14 15 16 sdi sdo t hsdo t dsdo b7 x d17 d16 d15 d14 d13 d12 d11 d10 16233-021 f igure 46 . register read timing diagram (x means dont care)
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 26 of 36 1 conversion result on d17:0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t cyc t sck t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh 1 t en cnv sck 1 2 3 4 5 0 0 1 0 1 0 1 0 0 wen r/w 0 1 0 1 addr[1:0] 9 10 11 12 13 14 15 16 17 18 sdi sdo b0 b1 b2 b3 b4 b5 b6 b7 t hsdo t dsdo t hcnvsck 1 the user must wait t conv time when reading back the conversion result and doing a register write at the same time. 16233-022 f igure 47 . register write timing diagram t cyc t sck t sck l t sckh t scnvsck sdi a sdo a /sdi b sdo b cnv sck t dis t cnvh 16233-020 0 0 command (0x14) 0 0 command (0x14) 0 0 command (0x14) 1 24 data (0xab) data (0xab) fi g ure 48 . register w rite timing diagram , d aisy -chain m ode
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 27 of 36 status word the 6 - bit status word can be appended to the end of a conversion result, and the default conditions of these bits are shown in table 15 . the status bits must be enabled in the register setting. when the overvoltage clamp flag ( ov ) is a 0, it indicates an overvoltage condition. the overvoltage clamp flag status bit updates on a per conversio n basis. the sdo line goes to high - z after the sixth status bit is clocked out (except in daisy - chain mode). the user is not required to clock out all status bits to start the next conversion. the serial interface timing for cs mode, 3- wire without busy indicator, including status bits, is shown in figure 49 . table 15. status bits (default conditions) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 overvoltage ( ov ) clamp flag s pan compression high - z mode turbo mode reserved reserved 16233-049 sdo d17 d16 d15 d1 d0 sck 1 2 3 16 17 18 t sck t sck l t sckh t hsdo t dsdo cn v conversion acquisition t cyc acquisition sdi = 1 t cnvh acq t en 23 24 t quiet2 status bits b[5:0] b1 t dis b0 22 t conv f igure 49 . cs mode, 3 - wire without busy indicator serial interface timing diagram, including status bits (sdi high)
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 28 of 36 cs mode, 3- wire turbo mode this mode is typically used when a single AD4002 / ad4006 / ad4010 device is connected to an spi - compatible digital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result , providing a lower sck rate. t he ad400 2 can achieve a throughput rate of 2 msps only when turbo mode is enabled and using a minimum sck rate of 75 mhz. with turbo mode enabled, the ad400 6 can also achieve its maximum throughput rate of 1 msps with a minimum sck rate of 25 mhz , and the ad40 10 can achieve its maximum throughput rate of 500 ksps with a minimum sck rate of 1 1 mhz . the connection diagram is shown in figure 50, and the corresponding timing diagram is s hown in figure 51 . AD4002/ ad4006/ ad4010 sdi sdo cnv sck convert data in clk digi tal host vio 16233-050 f igure 50 . cs mode, 3 - wire turbo mode connection diagram (sdi high) this mode replaces the 3 - wire with busy indicator mode by programming the tur bo mode bit , bit 1 (see tabl e 14 ). when sdi is forced high, a rising edge on cnv initiates a conversion. the pre vious conversion data is available to read after the cnv rising edge. t he user must wait t quiet1 time after c nv is brought high before bringing cnv low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the AD4002/ad4006/ad4010 enter the acquisition phase and power down. when cnv goes low, the msb is output to sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 1 8 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. sdi = 1 t cyc cnv acquisition acquisition t acq t sck t sck l conversion sck d0 d1 d15 d16 d17 sdo t en t hsdo 1 2 3 16 17 18 t dsdo t dis t sckh t quiet1 quiet2 conv 16233-029 f igure 51 . cs mode, 3 - wire turbo mode serial interface timing diagram (sdi high)
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 29 of 36 cs mode, 3- wire without busy indicator this mode is typically used when a single AD4002 / ad4006 / ad40 10 device is connected to an spi - compatible di gital host. the connection diagram is shown in figure 52 , and the corresponding timing diagram is shown in figure 53. AD4002/ ad4006/ ad4010 sdi sdo cnv sck convert data in clk digital host vio 16233-025 f igure 52 . cs mode, 3 - wire without busy indicator connection diagram (sdi high) w ith sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. after a conversion is in itiated, it continues until completion irrespective of the state of cnv. this feature can be useful, for instance, to brin g cnv low to select other spi devices, such as analog multiplexers ; however, cnv must be returned high before the minimum conversion t ime elapses and then held high for the maximum possible conversion time to avoid the generatio n of the busy signal indicator. when the conversion is complete, the AD4002/ad4006/ad4010 enter the acquisition phase and power down. when cnv goes low, the msb i s output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 1 8 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. there must not be any digital activity on sck during the conversion. sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 16 17 18 t sck t sck l t sckh hsdo t dsdo cnv conversion acquisition t cyc acquisition sdi = 1 t cnvh t acq t en t quiet2 t conv 16233-026 figure 53 . cs mode, 3 - wire without busy indicator serial interface timing diagram (sdi high)
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 30 of 36 cs mode, 3- wire with busy indicator this mode is typically used when a single AD4002 / ad4006 / ad40 10 device is connected to an spi - compatible digital host with an interrupt input ( irq ). the connection diagram is shown in figure 54 , and the corresponding timing diagram is shown in figure 55 . sdi sdo cnv sck convert d at a in clk digital host vio irq vio 1k? AD4002/ ad4006/ ad4010 14956-024 f igure 54 . cs mode, 3 - wire with busy indicator connection diagram (sdi high) with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion , irrespective of the state of cnv. prior to the minimum conversion time, cnv can select other spi device s, such as analog multiplexers; however, cnv m ust be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impeda nce. with a pull - up resistor of 1 k ? on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad400 2/ ad400 6/ ad40 10 then enter the acquisition phase and power down. the data bits a re then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad400 2 /ad400 6 /ad40 10 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch - up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. there must not be any digital activity on the sck during the conversion . sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sck l t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t quiet2 16233-028 f igure 55 . cs mode, 3 - wire with busy indicator serial interface timing diagram (sdi high)
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 31 of 36 cs mode, 4- wire turbo mode this mode is typically used when a single AD4002 / ad4006 / ad40 10 device is connected to an spi - compatible dig ital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result, giving a lower sck rate . the ad400 2 can achieve a throughput rate of 2 msps only when turbo mode is enabled and using a minimum sck rate of 7 5 mhz. with turbo mode enabled, the ad400 6 can also achieve its maximum throughput rate of 1 msps with a minimum sck rate of 2 5 mhz, and the ad40 10 can achieve its maximum throughput rate of 500 ksps with a minimum sck rate of 1 1 mhz. the co nnection diagram is shown in figure 56 , and the corresponding timing diagram is shown in figure 57. AD4002/ ad4006/ ad4010 sdi sdo cnv sck convert data in clk digital host irq vio 1k? cs1 16233-153 f igure 56 . cs mode, 4 - wire turbo mode connection diagram this mode replaces the 4- wire with busy indicator mode by programming the turbo mode bit , bit 1 (se e table 14 ). with sdi high, a rising edge on cnv initiates a conversion. the previous conversion data is available t o read after the cnv rising edge. the user must wait t quiet1 time after cnv is brought high before bringing sdi low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the ad400 2/ ad400 6/ ad40 10 enter the acquisition phase and power down. the adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. th e remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptabl e hold time. after the 1 8 th sck falling edge or when sdi goes high ( whichever occurs first ), sdo returns to high impedance. acquisition sdo sck acquisition sdi cnv t ssdicnv t hsdicnv t cyc t sck t sck l t en t hsdo 1 2 3 16 17 18 t dsdo t dis t sckh d17 d16 d15 d1 d0 t quiet1 t quiet2 t acq conversion t conv 16233-034 figure 57 . cs mode, 4 - wire turbo m ode timing diagram
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 32 of 36 cs mode, 4- wire without busy indicator this mode is typically used when multiple AD4002 / ad4006 / ad40 10 devices are connected to an spi - compatible digital host. a connection diagram example using two AD4002 / ad4006 / ad40 10 devices is shown in figure 58 , and the corresponding timing diagram is shown in figure 59. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces s do to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data read back. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi device s, such as analog multiplexers; however, sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad400 2/ ad400 6/ ad4 0 10 enter the acquisition phase and power down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 1 8 th sck falling edge or when sdi goes high ( whichever occurs first ), sdo retur ns to high impedance and another ad400 2/ ad400 6/ ad40 10 can be read. sdi sdo cnv sck device a convert data in clk digital host AD4002/ ad4006/ ad4010 AD4002/ ad4006/ ad4010 sdi sdo cnv sck device b cs1 cs2 16233-027 f igure 58 . cs mode, 4 - wire without busy indicator connection diagram sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 34 35 36 t hsdo t dsdo t en conversion acquisition t conv cyc t acq acquisition sdi (cs1) cnv t ssdicnv t hsdicnv d1 16 17 t sck t sck l t sckh d0 d17 d16 19 20 18 sdi (cs2) t quiet2 16233-031 f igure 59 . cs m ode, 4 - wire without busy indicator serial interface timing diagram
preliminary technical data AD4002 / ad4006 / ad4010 rev. pra | page 33 of 36 cs mode, 4- wire with busy indicator this mode is typically used when a single AD4002 / ad4006 / ad40 10 device is connected to an spi - compatible digital host with an interrupt input ( irq ), and when it is desired to keep cnv, which sample s the analog input, independent of the signal used to select the data reading. this independence is particularly important in applications where low jitter on cnv is d esired. the connection diagram is shown in figure 60 , and the corresponding timing diagram is shown in figure 61. AD4002/ ad4006/ ad4010 sdi sdo cnv sck convert data in clk digital host irq vio 1k? cs1 16233-060 f igure 60 . cs mode, 4 - wire with busy indicator connection diagram with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data read back. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi device s, such as analog multiplexers; however, sdi must be returned low before the minimum conversion time ela pses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull - up resistor of 1 k ? on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad400 2/ ad400 6/ ad40 10 then enter the acquisition phase and power down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or when sd i goes high (whichever occurs first) , sdo returns to high impedance. sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sck l t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv t quiet2 16233-033 f igure 61 . cs mode, 4 - wire with busy indicator serial interface timing diagram
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 34 of 36 daisy - chain mode use t his mode to daisy - chain m ultip le ad400 2 /ad400 6 /ad40 10 devices on a 3- wire or 4 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity . data read back is analogous to clocking a shift register. a connection diagram example using two AD4002 / ad4006 / ad40 10 devices is shown in figure 62 , and the corresponding timing diagram is shown in figure 63. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects daisy - chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad400 2 /ad400 6 /ad40 10 enter the acquisition phase and power down. the remaining data bits stored in the internal shift register are clocked out of s do by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck rising edges. each adc in the daisy - chain outputs its data msb first, and 1 8 n clocks are required to read back the n adcs. the data is valid on both sck edges. the maximum conversion rate is reduced because of the total readback time. it is possible to write to each adc register in daisy - chain mode. the timing diagram is shown in fi gure 48 . this mode requires 4- wire operation because data is clocked in on the sdi line with cnv held low. the same command byte and register data can be shifted through the entire chain to program all adcs in the chain with the same register contents , which re quires 8 (n + 1) clocks for n adcs. it is possible to write different register contents t o each adc in the chain by writing to the furthest adc in the chain , first using 8 (n + 1) clocks , and then the second furthest adc with 8 n clocks , and so forth until reaching the nearest adc in the chain , which require s 16 clocks for the command and register data . it is not possible to read register contents in daisy - chain mode ; however , the six status bits can be enabled if the user wants to determine the adc c onfiguration. note that enabling the status bits requires six extra clocks to clock out the adc result and the status bits per adc in the chain. tur b o mode cannot be used in daisy - chain mode. convert data in clk digital host device b device a AD4002/ ad4006/ ad4010 sdi sdo cnv sck sdi sdo cnv sck 16233-062 AD4002/ ad4006/ ad4010 f igure 62 . daisy - chain mode , conne ction diagram sdo a = sdi b d a 17 d b 17 d b 16 d b 15 d a 16 d a 15 d a 1 d a 0 d a 1 d a 0 d b 1 d b 0 sck 1 2 3 34 35 36 t ssdisck t hsdisck conversion acquisition t conv t cyc t acq acquisition cnv 16 17 t sck t sck l t sckh 19 20 18 sdi a = 0 sdo b d a 17 d a 16 t hsdo t dsdo t quiet2 t hsckcnv t dis t quiet2 t en 16233-037 f igure 63 . daisy - chain mode , serial interface timing diagram
preliminary technical data AD4002/ ad4006/ ad4010 rev. pra | page 35 of 36 layout guidelines the pcb that houses the AD4002/ad4006/ad4010 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the AD4002/ad4006/ad4010, with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD4002/ad4006/ad4010 is used as a shield. fast switching signals, such as cnv or clocks, must not run near analog signal paths. avoid crossover of digital and analog signals. at least one ground plane must be used. it can be common or split between the digital and analog sections. in the latter case, join the planes underneath the AD4002/ad4006/ad4010 devices. the AD4002/ad4006/ad4010 voltage reference input (ref) has a dynamic input impedance. decouple the ref pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to (ideally right up against) the ref and gnd pins and connect them with wide, low impedance traces. finally, decouple the vdd and vio power supplies of the AD4002/ad4006/ad4010 with ceramic capacitors, typically 0.1 f, placed close to the AD4002/ad4006/ad4010 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of the AD4002 layout following these rules is shown in figure 64 and figure 65. note that the ad4006/ ad4010 layout is equivalent to the AD4002 layout. evaluating the AD4002/ad4006/ad4010 performance other recommended layouts for the AD4002/ad4006/ad4010 are outlined in the user guide of the evaluation board for the AD4002 ( eval-AD4002fmcz ). the evaluation board package includes a fully assembled and tested evaluation board with the AD4002, documentation, and software for controlling the board from a pc via the eval-sdp-ch1z . the eval-AD4002fmcz can also be used to evaluate the ad4006/ad4010 by limiting the throughput to 1 msps/500 ksps in its software (see ug-1042). 16233-064 figure 64. example layout of the AD4002 (top layer) 16233-065 figure 65. example layout of the AD4002 (bottom layer)
AD4002 / ad4006 / ad4010 preliminary technical data rev. pra | page 36 of 36 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 f igure 66 . 10 - lead mi ni small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 coplanarity 0.08 top view side view bottom vie w 0.20 min pkg-004362 02-07-2017-c for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 indic at or area options (see detail a) detail a (jedec 95) f igure 67 . 10 - lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp - 10 - 9) dimensions shown in millimeters ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d16233 -0- 9/17(pra)

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